It is well recognized that it is desirable to be able to transmit synchronously digital signals from one node to another in a digital transmission system. However, if the average rate of transmission of bits from a node is not exactly equal to the average rate incoming to the node, errors occur. Such errors are defined as slips. A slip means that bits are arbitrarily deleted if the input transmission rate exceeds the output rate, or that bits are repeated or inserted arbitrarily if the input transmission rate is slower than the output rate. To assure synchronization and avoid slips, the nodes must be synchronized to a common reference signal. To this end, each node includes a local timing signal generator, commonly referred to as a local clock, which generates timing signals at a predetermined frequency. The local clock is adjusted to be in synchronization with a reference signal.
One known arrangement for realizing the desired synchronization is described in U.S. Pat. No. 4,305,045 issued to Reinhart Metz et al on Dec. 8, 1981. Disclosed are a frequency estimating and synthesizing arrangement that includes a programmable controller as part of a single phase lock loop to control digitally an oscillator for obtaining the desired synchronization of the local clock. A problem arises with such arrangements when the reference timing signal link to the node fails. In such an event, the digitally controlled oscillator is allowed to free run at the long-term average frequency known at the node at the time of the failure. Consequently, the free run stability of the digitally controlled oscillator is of critical importance in order to maintain performance objectives. Such arrangements typically included precision crystal oscillators which are controlled via a digital-to-analog converter. In such oscillator arrangements, all of the circuitry is typically enclosed in one or more oven chambers to provide a stable temperature environment. Desirable features of such arrangements include high digital control frequency resolution and high stability, among others. These features present conflicting design constraints which are difficult to accommodate. Moreover, the high stability constraint of such prior arrangement is expensive to obtain.